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参数资料
| 型号： | M4-128N/64-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC84 |
| 封装： | PLASTIC, LCC-84 |
| 文件页数： | 29/46页 |
| 文件大小： | 754K |
| 代理商： | M4-128N/64-15JC |
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MACH 4 Family
35
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequen-
cy. The selected “typical” pattern is a 16-bit up-down counter. This pattern lls the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type reg-
ister. Power/Speed are optimized to obtain the highest counter frequency and the lowest power.
The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The
lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power.
350
300
250
200
150
100
50
0
10
20
30
40
50
60
70
80
90
100
110
120
130
VCC = 5 V or 3.3 V, TA = 25 C
I CC
(mA)
Frequency (MHz)
17466G-066
M4(LV)-32/32
M4(LV)-64/32
M4(LV)-96/48
M4(LV)-128/64
M4(LV)-192/96
M4(LV)-256/128
Figure 18. MACH 4 ICC Curves at High Speed Mode
350
300
250
200
150
100
50
0
10
20
30
40
50
60
70
80
90
100
110
120
VCC = 5 V or 3.3 V, TA = 25 C
M4(LV)-32/32
I CC
(mA)
Frequency (MHz)
17466G-065
M4(LV)-64/32
M4(LV)-96/48
M4(LV)-128/64
M4(LV)-192/96
M4(LV)-256/128
Figure 19. MACH 4 ICC Curves at Low Power Mode
相关PDF资料 |
PDF描述 |
|---|---|
| M4-128N/64-18JI | High Performance E 2 CMOS In-System Programmable Logic |
| M4-128N/64-7JC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-192/96-12VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-192/96-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-12VI48 | High Performance E 2 CMOS In-System Programmable Logic |
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