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参数资料
| 型号： | M4-64/32-12VC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 8/46页 |
| 文件大小： | 754K |
| 代理商： | M4-64/32-12VC |
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16
MACH 4 Family
I/O Cell
path, and ip-op (except MACH 4 devices with 1:1 macrocell-I/O cell ratio.) An individual
output enable product term is provided for each I/O cell. The feedback signal drives the input
switch matrix.
The I/O cell (Figure 10) contains a ip-op, which provides the capability for storing the input
in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and
registered versions of the input are sent to the input switch matrix. This allows for such functions
as “time-domain-multiplexed” data comparison, where the rst data value is stored, and then the
second data value is put on the I/O pin and compared with the previous stored value.
Note that the ip-op used in the MACH 4 I/O cell is independent of the ip-ops in the
macrocells. It powers up to a logic low.
Zero-Hold-Time Input Register
The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated
with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse
increases the data path setup delays to input storage elements, matching equivalent delays in
the clock path. When the fuse is erased, the setup time to the input storage element is minimized.
This feature facilitates doing worst-case designs for which data is loaded from sources which
have low (or zero) minimum output propagation delays from clock edges.
Input Switch Matrix
matrix. Without the input switch matrix, each input and feedback signal has only one way to
enter the central switch matrix. The input switch matrix provides additional ways for these
signals to enter the central switch matrix.
D/L
Q
Block CLK3
Block CLK2
Block CLK1
Block CLK0
To
Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
17466G-017
17466G-018
Figure 10. I/O Cell for MACH 4 Devices with 2:1
Macrocell-I/O Cell Ratio
Figure 11. I/O Cell for MACH 4 Devices with 1:1
Macrocell-I/O Cell Ratio
To
Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
Power-up reset
相关PDF资料 |
PDF描述 |
|---|---|
| M4-64/32-12VC48 | High Performance E 2 CMOS In-System Programmable Logic |
| M4-64/32-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4-64/32-12VI48 | High Performance E 2 CMOS In-System Programmable Logic |
| M4-64/32-15JC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-64/32-15VC | High Performance E 2 CMOS In-System Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M4644 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000' |
| M4644 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 500' |
| M4644 SL005 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 100' |
| M4644 SL199 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000=1000' |
| M4644-SL001 | 制造商:Alpha Wire 功能描述: |
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