参数资料
型号: M4-96/48-15VC
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 15 ns, PQFP100
封装: TQFP-100
文件页数: 3/46页
文件大小: 754K
代理商: M4-96/48-15VC
MACH 4 Family
11
The ip-op can be congured as a D-type or T-type latch. J-K or S-R registers can be
synthesized. The primary ip-op congurations are shown in Figure 6, although others are
possible. Flip-op functionality is dened in Table 8. Note that a J-K latch is inadvisable as it will
cause oscillation if both J and K inputs are HIGH.
DQ
AP AR
DQ
AP AR
LQ
AP AR
LQ
AP AR
G
TQ
AP AR
17466G-011
Figure 6. Primary Macrocell Congurations
g. Combinatorial with programmable polarity
a. D-type with XOR
b. D-type with programmable D polarity
c. Latch with XOR
d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR
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