Symbol
Parameter
Min
Max
Unit
fSCL
SCL Clock Frequency
0
100
kHz
tLOW
Clock Low Period
4.7
s
tHIGH
Clock High Period
4
s
tR
SDA and SCL Rise Time
1
s
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
4
s
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
4.7
s
tSU:DAT
Data Setup Time
250
ns
tHD:DAT
(1)
Data Hold Time
0
s
tSU:STO
STOP Condition Setup Time
4.7
s
tBUF
Time the bus must be free before a new transmission can start
4.7
s
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
Table 10. AC Characteristics
(TA = –40 to 85
°C; VCC = 2.0V to 5.5V)
WRITE MODE
In this mode the master transmitter transmits to the
M41T00 slave receiver. Bus protocol is shown in
Figure 10. Following the START condition and
slave address, a logic ’0’ (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the
internal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The M41T00 slave re-
ceiver will send an acknowledge clock to the master
transmitter after it has received the slave address
and again after it has received the word address
and each data byte (see Figure 9).
READ MODE
In this mode, the master reads the M41T00 slave
after setting the slave address (see Figure 11).
Following the write mode control bit (R/W = 0) and
the acknowledge bit, the word address An is written
to the on-chip address pointer. Next the START
condition and slave address are repeated, followed
by the READ mode control bit (R/W = 1). At this
point, the master transmitter becomes the master
receiver. The data byte which was addressed will
be transmitted and the master receiver will send an
acknowledge bit to the slave transmitter. The ad-
dress pointer is only incremented on reception of
an acknowledge bit. The M41T00 slave transmitter
will now place the data byte at address An + 1 on the
bus. The master receiver reads and acknowledges
the new byte and the address pointer is incre-
mented to An + 2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be imple-
mented, whereby the master reads the M41T00
slave without first writing to the (volatile) address
pointer. The first address that is read is the last one
stored in the pointer, see Figure 12.
7/15
M41T00