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M41T56
Clock Calibration
The M41T56 is driven by a quartz-controlled oscil-
lator with a nominal frequency of 32,768 Hz. The
devices are tested not to exceed 35ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M41T56 improves to better than +1/–2 ppm
at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 17, page 16). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome “trim” capac-
itors. The M41T56 design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 17, page 16. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration Byte
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register (Addr 7). This
byte can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minutes cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increments in the Calibration
Byte would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M41T56 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accessed the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the
Control Register, is set to a '1,' and the oscillator is
running at 32,768 Hz, the FT/OUT pin of the de-
vice will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator
frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would in-
dicate a +20ppm oscillator frequency error, requir-
ing a –10(XX001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
Output Driver Pin
When the FT Bit is not set, the FT/OUT pin be-
comes an output driver that reflects the contents of
D7 of the Control Register. In other words, when
D6 of location 7 is a '0' and D7 of location 7 is a '0'
and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which re-
quires an external pull-up resistor.
Initial Power-on Defaults
Upon initial application of power to the device, the
FT Bit will be set to a '0' and the OUT Bit will be set
to a '1.' All other Register bits will initially power-on
in a random state.