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参数资料
| 型号： | M41T80M6F |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 0.150 INCH, LEAD FREE, PLASTIC, SO1C-8 |
| 文件页数： | 2/25页 |
| 文件大小： | 343K |
| 代理商： | M41T80M6F |
Operation
M41T80
Doc ID 9074 Rev 4
2.2
READ mode
In this mode the master reads the M41T80 slave after setting the slave address (Figure 8:
READ mode sequence). Following the WRITE mode control bit (R/W=0) and the
acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an acknowledge
bit to the slave transmitter. The address pointer is only incremented on reception of an
acknowledge clock. The M41T80 slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the M41T80
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9: Alternative READ mode sequence).
Table 2.
AC characteristics
Sym
Parameter(1)
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where
noted).
Min
Typ
Max
Units
fSCL
SCL clock frequency
0
400
kHz
tLOW
Clock low period
1.3
s
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of
the falling edge of SCL.
Data setup time
100
ns
tHD:DAT
Data hold time
0
s
tSU:STO
STOP condition setup time
600
ns
tBUF
Time the bus must be free before a new
transmission can start
1.3
s
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