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参数资料
| 型号： | M440T513Y-15ZA9 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PBGA168 |
| 封装： | PLASTIC, BGA-168 |
| 文件页数： | 3/26页 |
| 文件大小： | 453K |
| 代理商： | M440T513Y-15ZA9 |
11/26
M440T513Y
Memory WRITE Mode
The M440T513Y is in the WRITE Mode whenever
any or all of W1-4 (WRITE Enable Byte 1 to 4) and
any corresponding E1-4 are in a low state after the
address inputs are stable. Thus a Byte WRITE (8-
bit), Word WRITE (16-bit) or Long Word WRITE
(32-bit) may be performed. The start of a WRITE
is referenced from the latter occurring falling edge
of W1-4 or E1-4. A WRITE is terminated by the
earlier rising edge of W1-4 or E1-4. The addresses
must be held valid throughout the cycle. E1-4 or
W1-4 must return high for a minimum of tEHAX
from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVWH prior to the end
of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E1-4 and G, a low on
W1-4 will disable the outputs tWLQZ after W1-4
falls.
Clock WRITE Mode
The clock is in the WRITE Mode whenever WC
(Clock WRITE Enable) and EC (Clock Chip En-
able) are in the low state after the address inputs
are stable. The start of a WRITE is referenced
from the latter occurring falling edge of WC or EC.
A WRITE is terminated by the earlier rising edge of
WC or EC. The addresses must be held valid
throughout the cycle. EC or WC must return high
for a minimum of tEHAX from Chip Enable Clock or
tWHAX from WRITE Enable Clock prior to the initi-
ation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and
remain valid for tWHDX afterward. GC should be
kept high during WRITE cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on EC and GC a low on WC will
disable the outputs tWLQZ after WC falls. See sec-
tion on Reading and Setting the Clock under
CLOCK OPERATION for more details.
Figure 10. Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled
Note: Output Enable (G) = Low
AI07016
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A18
E1 - E4
W1 - W4
DQ0-DQ31
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
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相关代理商/技术参数 |
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| M440X40MMN70 | 制造商:n/a 功能描述:Ships in 2 days |
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