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参数资料
| 型号： | M44C092-V |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SSO-20 |
| 文件页数： | 57/80页 |
| 文件大小： | 609K |
| 代理商： | M44C092-V |
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M44C092–V
Rev. A2, 08-Nov-01
60 (80)
Serial Interface Status and Control Register (SISC)
Primary register address: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
SISC
write
MCL
RACK
SIM
IFN
Reset value: 1111b
SISC
read
– – –
TACK
ACT
SRDY
Reset value: xxxxb
MCL
Multi-Chip Link activation
MCL = 1,
multi-chip link disabled. This bit has to be set to ’0’ during transactions to/from
EEPROM of the M44C092–V
MCL = 0,
connnects SC and SD additional to the internal multi-chip link pads
RACK
Receive ACKnowledge status/control bit for I2C mode
RACK = 0,
transmit acknowledge in next receive telegram
RACK = 1,
transmit no acknowledge in last receive telegram
TACK
Transmit ACKnowledge status/control bit for I2C mode
TACK = 0,
acknowledge received in last transmit telegram
TACK = 1,
no acknowledge received in last transmit telegram
SIM
Serial Interrupt Mask
SIM = 1,
disable interrupts
SIM = 0,
enable serial interrupt. An interrupt is generated.
IFN
Interrupt FuNction
IFN = 1,
the serial interrupt is generated at the end of telegram
IFN = 0,
the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes
empty/full in transmit/receive mode)
SRDY
Serial interface buffer ReaDY status flag
SRDY = 1,
in receive mode:
receive buffer empty
in transmit mode:
transmit buffer full
SRDY = 0,
in receive mode:
receive buffer full
in transmit mode:
transmit buffer empty
ACT
Transmission ACTive status flag
ACT = 1,
transmission is active, i.e., serial data transfer. Stop or start conditions are currently in
progress.
ACT = 0,
transmission is inactive
Serial Transmit Buffer (STB) – Byte Write
Primary register address: ’9’hex
STB
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting
with the most significant bit.
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