参数资料
型号: M470L6423EN0-CB3
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512MB Unbuffered SODIMM(based on sTSOP)
中文描述: 512MB的无缓冲的SODIMM(基于sTSOP)
文件页数: 8/13页
文件大小: 145K
代理商: M470L6423EN0-CB3
DDR SDRAM
512MB Unbuffered SODIMM(based on sTSOP)
Rev. 1.3 March. 2004
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25
°
C, f=1MHz)
Parameter
Symbol
M470L6423EN0
Unit
Min
38
38
36
36
12
12
12
Max
47
47
44
40
14
14
14
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )
CIN1
pF
Input capacitance(CKE0, CKE1)
CIN2
pF
Input capacitance(CS0, CS1)
CIN3
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
pF
Input capacitance(DM0~DM7)
CIN5
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
pF
Data input/output capacitance (CB0~CB7)
Cout2
pF
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
VREF + 0.31
V
2
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
V
V
V
3
3
1
VREF - 0.31
VDDQ+0.6
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