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参数资料
| 型号： | M470T2953CZ0-D5 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR2 Unbuffered SODIMM |
| 中文描述： | 无缓冲DDR2内存的SODIMM |
| 文件页数： | 2/20页 |
| 文件大小： | 270K |
| 代理商： | M470T2953CZ0-D5 |
Rev. 1.1 Mar. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 Unbuffered SODIMM Ordering Information
DDR2 SDRAM
Note: “Z” of Part number stand for Lead-free products.
Part Number
Density
Organization
Component Composition
Number of
Rank
Height
M470T3354CZ0-C(L)D6/E6/D5/CC
256MB
32Mx64
32Mx16(K4T51163QC-C(L)D6/E6/D5/CC)*4
1
30mm
M470T6554CZ0-C(L)D6/E6/D5/CC
512MB
64Mx64
32Mx16(K4T51163QC-C(L)D6/E6/D5/CC)*8
2
30mm
M470T2953CZ0-C(L)D6/E6/D5/CC
1GB
128Mx64
64Mx8(K4T51083QC-C(L)D6/E6/D5/CC)*16
2
30mm
Features
Performance range
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin
4 independent internal banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
PASR(Partial Array Self Refresh)
Average Refesh Period 7.8us at lower a T
CASE
85
°
C, 3.9us at 85
°
C < T
CASE
< 95
°
C
- support
High Temperature Self-Refresh rate enable feature
Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA 32Mx16
-
RoHS Compliant
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
D6(DDR2-667)
E6(DDR2-667)
D5(DDR2-533)
CC(DDR2-400)
Unit
Speed@CL3
400
400
400
400
Mbps
Speed@CL4
667
533
533
400
Mbps
Speed@CL5
667
667
533
-
Mbps
CL-tRCD-tRP
4-4-4
5-5-5
4-4-4
3-3-3
CK
Address Configuration
Organization
64Mx8(512Mb)
based Module
32Mx16(512Mb)
based Module
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA1
Auto Precharge
A10
A0-A12
A0-A9
BA0-BA1
A10
相关PDF资料 |
PDF描述 |
|---|---|
| M470T2953CZ0-E6 | DDR2 Unbuffered SODIMM |
| M470T6554CZ0 | DDR2 Unbuffered SODIMM |
| M48T02-150PC1 | 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM |
| M48T02-200PC1 | 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM |
| M48T02-70PC1 | 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M470T2953CZ0-E6 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM |
| M470T2953CZ3-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953CZ3-CD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953CZ3-CD500 | 制造商:Samsung Semiconductor 功能描述:512 DDR SDRAM MODUL X64 BOC(LF) - Trays |
| M470T2953CZ3-CE6 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
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