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参数资料
| 型号： | M470T6554CZ0-CE6 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| 中文描述： | 内存缓冲的SODIMM 200pin缓冲的SODIMM上的512Mb基于C模具64非ECC |
| 文件页数： | 2/18页 |
| 文件大小： | 328K |
| 代理商： | M470T6554CZ0-CE6 |
Rev. 1.2 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
DDR2 Unbuffered SODIMM Ordering Information
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Part Number
Density
Organization
Component Composition
Number of Rank
Height
M470T3354CZ3-C(L)E7/E6/D5/CC
256MB
32Mx64
32Mx16(K4T51163QC)*4
1
30mm
M470T3354CZ0-C(L)E7/E6/D5/CC
256MB
32Mx64
32Mx16(K4T51163QC)*4
1
30mm
M470T6554CZ3-C(L)E7/E6/D5/CC
512MB
64Mx64
32Mx16(K4T51163QC)*8
2
30mm
M470T6554CZ0-C(L)E7/E6/D5/CC
512MB
64Mx64
32Mx16(K4T51163QC)*8
2
30mm
M470T2953CZ3-C(L)E7/E6/D5/CC
1GB
128Mx64
64Mx8(K4T51083QC)*16
2
30mm
M470T2953CZ0-C(L)E7/E6/D5/CC
1GB
128Mx64
64Mx8(K4T51083QC)*16
2
30mm
Features
Performance range
JEDEC standard 1.8V ± 0.1V Power Supply
V
DDQ
= 1.8V ± 0.1V
200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
PASR(Partial Array Self Refresh)
Average Refresh Period 7.8us at lower than a T
CASE
85
°
C, 3.9us at 85
°
C < T
CASE
< 95
°
C
-
support
High Temperature Self-Refresh rate enable feature
Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
E7 (DDR2-800)
E6 (DDR2-667)
D5 (DDR2-533)
CC (DDR2-400)
Unit
Speed@CL3
400
400
400
400
Mbps
Speed@CL4
533
533
533
400
Mbps
Speed@CL5
800
667
533
-
Mbps
CL-tRCD-tRP
5-5-5
5-5-5
4-4-4
3-3-3
CK
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
64Mx8(512Mb) based Module
A0-A13
A0-A9
BA0-BA1
A10
32Mx16(512Mb) based Module
A0-A12
A0-A9
BA0-BA1
A10
相关PDF资料 |
PDF描述 |
|---|---|
| M470T6554CZ0-CE7 | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLCC | PATCHCORD SQ SCKT-ALLIG CLIP RED |
| M470T6554CZ0-CLD5 | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE6 | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE7 | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M470T6554CZ0-CE7 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE6 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE7 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
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