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参数资料
| 型号： | M470T6554CZ0-CLCC |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PATCHCORD SQ SCKT-ALLIG CLIP RED |
| 中文描述： | 内存缓冲的SODIMM 200pin缓冲的SODIMM上的512Mb基于C模具64非ECC |
| 文件页数： | 9/18页 |
| 文件大小： | 328K |
| 代理商： | M470T6554CZ0-CLCC |
Rev. 1.2 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
V
DDQ
V
IH
(AC) min
V
IH
(DC) min
V
REF
V
IL
(DC) max
V
IL
(AC) max
V
SS
< AC Input Test Signal Waveform >
V
SWING(MAX)
delta TR
delta TF
V
REF
- V
IL
(AC) max
delta TF
Falling Slew =
Rising Slew =
V
IH
(AC) min - V
REF
delta TR
Operating Temperature Condition
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95
°
C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Input AC Logic Level
AC Input Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
IH/IL
(AC)
level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH
(AC) min for rising edges and the range from V
REF
to V
IL
(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V
IL
(AC) to V
IH
(AC) on the positive transitions and V
IH
(AC) to V
IL
(AC) on the negative
transitions.
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°
C
1, 2, 3
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH
(DC)
V
IL
(DC)
DC input logic high
V
REF
+ 0.125
V
DDQ
+ 0.3
V
DC input logic low
- 0.3
V
REF
- 0.125
V
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units
Min.
Max.
Min.
Max.
V
IH
(ac)
V
IL
(ac)
ac input logic high
V
REF
+ 0.250
-
V
REF
+ 0.200
V
ac input logic low
-
V
REF
- 0.250
V
REF
- 0.200
V
Symbol
Condition
Value
Units
Notes
V
REF
Input reference voltage
0.5 * V
DDQ
1.0
V
1
V
SWING(MAX)
SLEW
Input signal maximum peak to peak swing
V
1
Input signal minimum slew rate
1.0
V/ns
2, 3
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| M470T6554CZ0-CLD5 | DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M470T6554CZ0-CLD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE6 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-CLE7 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T6554CZ0-D5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM |
| M470T6554CZ0-E6 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM |
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