参数资料
型号: M470T6554CZ0
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR2 Unbuffered SODIMM
中文描述: 无缓冲DDR2内存的SODIMM
文件页数: 13/20页
文件大小: 270K
代理商: M470T6554CZ0
Rev. 1.1 Mar. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-667/533/400
(0
°
C < T
OPER
< 95
°
C; V
DDQ
= 1.8V + 0.1V; V
DD
= 1.8V + 0.1V)
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command
time
tRFC
75
105
127.5
195
327.5
ns
Average periodic refresh interval
tREFI
0
°
C
T
CASE
85
°
C
7.8
7.8
7.8
7.8
7.8
μ
s
85
°
C
<
T
CASE
95
°
C
3.9
3.9
3.9
3.9
3.9
μ
s
Speed
DDR2-667(D6)
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
Units
Bin
(CL - tRCD - tRP)
4 - 4 - 4
5 - 5 - 5
4 - 4 - 4
3 - 3 - 3
Parameter
min
max
min
max
min
max
min
max
tCK, CL=3
5
8
5
8
5
8
5
8
ns
tCK, CL=4
3
8
3.75
8
3.75
8
5
8
ns
tCK, CL=5
3
8
3
8
3.75
8
-
-
ns
tRCD
12
15
15
15
ns
tRP
12
15
15
15
ns
tRC
51
54
55
55
ns
tRAS
39
70000
39
70000
40
70000
40
70000
ns
Parameter
Symbol
DDR2-667
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
min
max
DQ output access time
from CK/CK
tAC
-450
+450
-500
+500
-600
+600
ps
DQS output access
time from CK/CK
tDQSCK
-400
+400
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL
, tCH)
x
min(tCL
, tCH)
x
min(tCL
, tCH)
x
ps
Clock cycle time, CL=x
tCK
3000
8000
3750
8000
5000
8000
ps
DQ and DM input hold
time
tDH(base)
175
x
225
x
275
x
ps
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