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参数资料
| 型号： | M48T128Y-85PM1TR |
| 厂商： | 意法半导体 |
| 元件分类： | SRAM |
| 英文描述： | 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| 中文描述： | 3.3 - 5V的1兆位的SRAM 128KB的x8计时器 |
| 文件页数： | 21/22页 |
| 文件大小： | 340K |
| 代理商： | M48T128Y-85PM1TR |
M48T128Y, M48T128V*
8/22
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
AI02382
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI02383
tAVAV
tEHAX
tDVEH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T128YPM | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T129 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T129V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T129V-70CS1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T129V-70PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 1 Mbit (128 Kbit x 8) TIMEKEEPER SRAM |
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