参数资料
型号: M48T212A-85MH1
厂商: 意法半导体
英文描述: 3.3V TIMEKEEPER CONTROLLER
中文描述: 3.3计时控制器
文件页数: 10/20页
文件大小: 165K
代理商: M48T212A-85MH1
M48T212A
10/20
Table 12. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
WRITE MODE
The M48T212A is in the Write Mode whenever W
(Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of t
EHAX
from Chip Enable
or t
WHAX
from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
t
DVWH
prior to the end of write and remain valid for
t
WHDX
afterward.
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs t
WLQZ
after W falls.
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data will be written into the device. When EX is low
(and E is high) an external SRAM location is se-
lected.
Note:
Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
DATA RETENTION MODE
With valid V
CC
applied, the M48T212A can be ac-
cessed as described above with read or write cy-
cles. Should the supply voltage decay, the
M48T212A will automatically deselect, write pro-
tecting itself (and any external SRAM) when V
CC
falls between V
PFD
(max) and V
PFD
(min). This is
accomplished by internally inhibiting access to the
clock registers via the E signal. At this time, the
Reset pin (RST) is driven active and will remain
active until V
CC
returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1
CON
and E2
CON
to a high level.
This level is within 0.2V of the V
BAT
. E1
CON
and
E2
CON
will remain at this level as long as V
CC
re-
mains at an out-of tolerance condition.
When V
CC
falls below the level of the battery
(V
BAT
), power input is switched from the V
CC
pin
to the battery and the clock registers and external
SRAM are maintained from the attached battery
supply. All outputs become high impedance. The
V
OUT
pin is capable of supplying 100μA of current
to the attached memory with less than 0.3V drop
under this condition. On power up, when V
CC
re-
turns to a nominal value, write protection contin-
ues for 200ms (max) by inhibiting E1
CON
or
E2
CON
.
Figure 9. Alarm Interrupt Reset Waveforms
AI03021
A0-A3
ACTIVE FLAG BIT
ADDRESS 0h
IRQ/FT
HIGH-Z
1h
Fh
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M48T212Y-70MH6TR Shielded Multiconductor Cable; Number of Conductors:5; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Conductor Material:Copper; Temperature Max:80 C RoHS Compliant: Yes
M48T212YSH Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Red; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Conductor Plating:Tin RoHS Compliant: Yes
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