参数资料
型号: M48T212AMH
厂商: 意法半导体
英文描述: 3.3V TIMEKEEPER CONTROLLER
中文描述: 3.3计时控制器
文件页数: 13/20页
文件大小: 165K
代理商: M48T212AMH
13/20
M48T212A
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M48T212A sets the WDF (Watchdog Flag) and
generates a watchdog interrupt or a microproces-
sor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a ‘1’, the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog register and
the FT bit will reset to a ‘0’ at the end of a Watch-
dog time-out when the WDS bit is set to a ‘1’.
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
2. the microprocessor can perform a write of the
Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to V
SS
if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register 0h).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog function prevails and the
frequency test function is denied.
Figure 10. Back-Up Mode Alarm Waveforms
AI03622
VCC
VPFD (max)
VPFD (min)
IRQ/FT
HIGH-Z
AFE bit/ABE bit
AF bit in Flags Register
HIGH-Z
tREC
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