参数资料
型号: M48T212Y-85MH6
厂商: 意法半导体
英文描述: Shielded Multiconductor Cable; Number of Conductors:7; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid RoHS Compliant: Yes
中文描述: 5V/3.3V计时[控制器
文件页数: 13/23页
文件大小: 150K
代理商: M48T212Y-85MH6
13/23
M48T212Y, M48T212V
TIMEKEEPER REGISTERS
The M48T212Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Flag, and Control data. These registers are mem-
ory locationswhich contain external (user accessi-
ble) and internal copies of the data (usually
referred to as BiPORT
TM
TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data in Binary Format.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted beforeclock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cellsin the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ‘1’ is written to the
READ bit, D6 in the Control Register (8h). As long
as a ‘1’ remains inthat position, updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a ‘0’.
Setting the Clock
Bit D7 of the Control Register (8h) is the WRITE
bit. Setting the WRITE bit to a ‘1’, like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 13).
Resetting the WRITE bit to a ‘0’ then transfers the
values of all time registers(Fh-9h, 1h) to theactual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE bit is reset, the
next clock update will occur one second later.
Note:
Upon power-up following a power failure,
the READ bit will automatically be set to a ‘1’. This
will prevent the clock from updating the TIME-
KEEPER registers, and will allow the user to read
the exact time of the power-down event.
Resetting theREAD Bitto a ‘0’ will allow the clock
to update these registers with the current time.
The WRITE Bit will be reset to a ‘0’ upon power-
up.
Figure 10. Back-Up Mode Alarm Waveforms
AI03622
VCC
VPFD(max)
VPFD(min)
IRQ/FT
HIGH-Z
AFE bit/ABE bit
AF bit in Flags Register
HIGH-Z
tREC
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