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参数资料
| 型号： | M48T251V-70PM1 |
| 厂商： | 意法半导体 |
| 英文描述： | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| 中文描述： | 5.0或3.3V，4096K与幻象计时器的SRAM |
| 文件页数： | 11/24页 |
| 文件大小： | 366K |
| 代理商： | M48T251V-70PM1 |
11/24
M48T251Y, M48T251V
Data Retention Mode
Data can be read or written only when V
CC
is
greater than V
PFD
. When V
CC
is below V
PFD
(the
point at which write protection occurs), the clock
registers and the SRAM are blocked from any ac-
cess. When V
CC
falls below the Battery Switch
Over threshold (V
SO
), the device is switched from
V
CC
to battery backup (V
BAT
). RTC operation and
SRAM data are maintained via battery backup un-
til power is stable. All control, data, and address
signals must be powered down when V
CC
is pow-
ered down.
The lithium power source is designed to provide
power for RTC activity as well as RTC and RAM
data retention when V
CC
is absent or unstable.
The capability of this source is sufficient to power
the device continuously for the life of the equip-
ment into which it has been installed. For specifi-
cation purposes, life expectancy is ten (10) years
at 25°C with the internal oscillator running without
V
CC
. Each unit is shipped with its energy source
disconnected, guaranteeing full energy capacity.
When V
CC
is first applied at a level greater than
V
PFD
, the energy source is enabled for battery
backup operation. The actual life expectancy will
be much longer if no battery energy is used (e.g.,
when V
CC
is present).
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is estab-
lished by pattern recognition of a serial bit-stream
of 64 bits which must be matched by executing 64
consecutive WRITE cycles containing the proper
data on DQ0.
All accesses which occur prior to recognition of the
64-bit pattern are directed to memory.
After recognition is established, the next 64 READ
or WRITE cycles either extract or update data in
the clock while disabling the memory.
Data transfer to and from the timekeeping function
is accomplished with a serial bit-stream under con-
trol of Chip Enable (CE), Output Enable (OE), and
WRITE Enable (WE). Initially, a READ cycle using
the CE and OE control of the clock starts the pat-
tern recognition sequence by moving the pointer to
the first bit of the 64-bit comparison register (see
Figure 8., page 12
).
Next, 64 consecutive WRITE cycles are executed
using the CE and WE control of the device. These
64 WRITE cycles are used only to gain access to
the clock. Therefore, any address to the memory
is acceptable. However, the WRITE cycles gener-
ated to gain access to the Phantom Clock are also
writing data to a location in the mated RAM. The
preferred way to manage this requirement is to set
aside just one address location in RAM as a Phan-
tom Clock scratch pad.
When the first WRITE cycle is executed, it is com-
pared to Bit 1 of the 64-bit comparison register. If
a match is found, the pointer increments to the
next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all of the
bits in the comparison register have been
matched. With a correct match for 64-bits, the
Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The
next 64 cycles will cause the Phantom Clock to ei-
ther receive or transmit data on DQ0, depending
on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be
interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer se-
quence to the Phantom Clock.
相关PDF资料 |
PDF描述 |
|---|---|
| M48T251V-70PM1TR | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251V-85PM1 | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251V-85PM1TR | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251V | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251VPM | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T251V-70PM1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251V-85PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251V-85PM1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251VPM | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
| M48T251Y | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
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