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参数资料
| 型号： | M48T35-70PC6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| 封装： | 0.600 INCH, CAPHAT, PLASTIC, DIP-28 |
| 文件页数： | 17/18页 |
| 文件大小： | 140K |
| 代理商： | M48T35-70PC6 |
M48T35, M48T35Y
8/18
Table 9. Write Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T35 / M48T35Y
Unit
-70
Min
Max
tAVAV
Write Cycle Time
70
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
50
ns
tELEH
Chip Enable Low to Chip Enable High
55
ns
tWHAX
Write Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
30
ns
tDVEH
Input Valid to Chip Enable High
30
ns
tWHDX
Write Enable High to Input Transition
5
ns
tEHDX
Chip Enable High to Input Transition
5
ns
tWLQZ
(1, 2)
Write Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to Write Enable High
60
ns
tAVEH
Address Valid to Chip Enable High
60
ns
tWHQX
(1, 2)
Write Enable High to Output Transition
5
ns
DATA RETENTION MODE
With valid VCC applied, the M48T35/35Y operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as "don't care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T35/35Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35/35Y
for an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues until VCC
reaches VPFD (min) plus tREC (min). E should be
kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to processor stabili-
zation. Normal RAM operation can resume tREC
after VCC exceeds VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T35-70PC6E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35-70PC6F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35-70PC6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35-70PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35-70PM1E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
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