参数资料
型号: M48T37V-70MH1
厂商: 意法半导体
英文描述: 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
中文描述: 3.3 - 5V的256千位的32KB的SRAM x8计时器
文件页数: 10/20页
文件大小: 128K
代理商: M48T37V-70MH1
M48T37Y, M48T37V
10/20
POWER-ON RESET
The M48T37Y/37V continuously monitors V
CC
.
When V
CC
falls to the power fail detect trip point,
the RSTpulls low (open drain) and remains lowon
power-up for 40ms to 200ms after V
CC
passes
V
PFD
. RST is valid for all V
CC
conditions.The RST
pin is an open drain output and an appropriate re-
sistor to V
CC
should be chosen to control rise time.
PROGRAMMABLE INTERRUPTS
The M48T37Y/37V provides two programmable
interrupts; an alarm and a watchdog. When an in-
terrupt condition occurs, the M48T37Y/37V sets
the appropriate flag bit in the flag register 7FF0h.
The interrupt enable bits in (AFE and ABE) in
7FF6h and the Watchdog Steering (WDS) bit in
7FF7h allow the interrupt to activate the IRQ/FT
pin.
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
condition resetwill not occur unless the addresses
are stable at the flag location for at least 15ns
while the device is in the read mode as shown in
Figure 11.
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10k
recommended) to
V
CC
. The pin remains in the high impedance state
unless an interrupt occurs or the frequency test
mode is enabled.
Figure 8. Chip Enable Controlled, Write AC Waveforms
Figure 9. Clock Calibration
AI00927
tAVAV
tEHAX
tDVEH
A0-A14
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
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