参数资料
型号: M48T37Y-70MH6TR
厂商: 意法半导体
英文描述: TRANS PREBIASED DUAL PNP SOT-363
中文描述: 3.3 - 5V的256千位的32KB的SRAM x8计时器
文件页数: 12/20页
文件大小: 128K
代理商: M48T37Y-70MH6TR
M48T37Y, M48T37V
12/20
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ‘1’ indi-
cates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ‘1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068or –2.034 ppm of adjustment
per calibration step in the calibration register. As-
suming that the oscillator is in fact running at ex-
actly 32,768 Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of theseconds register. Setting it to
a ‘1’ stops the oscillator. When reset to a ’0’, the
M48T37Y/37V oscillator starts within one second.
Note
: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Calibrating the Clock
The M48T37Y/37V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed
±
35 ppm
(parts per million) oscillator frequency error at
25
°
C, which equates to about
±
1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/37V improves to bet-
ter than +1/–2 ppm at 25
°
C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T37Y/37V design, however, employs pe-
riodic counter correction. The calibration circuit
adds or subtractscounts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
Figure 10. Crystal Accuracy Across Temperature
AI00999
–160
0
10
20
30
40
50
60
70
Frequency (ppm)
20
Temperature
°
C
80
–10
–20
–30
–40
–100
–120
–140
–40
–60
–80
0
–20
F= -0.038
F
(T - T
0
)
2
±
10%
ppm
C
2
T
0
= 25
°
C
相关PDF资料
PDF描述
M48T37Y-70MH6 TRANS PREBIAS DUAL COMP SOT-563
M48T37Y-70MH1TR TRANS PREBIASED DUAL COMP SOT363
M48T37Y-10MH6TR TRANS PREBIASED DUAL COMP SOT363
M48T37Y-10MH6 TRANS PREBIASED DUAL COMP SOT363
M48T37Y-10MH1TR 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
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