参数资料
型号: M48T513V-70CS1
厂商: 意法半导体
英文描述: 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM
中文描述: 3.3 - 5V的4兆位的SRAM 512KB的x8计时器
文件页数: 12/23页
文件大小: 145K
代理商: M48T513V-70CS1
M48T513Y, M48T513V
12/23
RESET INPUT (RSTIN)
The M48T513Y/V provides an independent input
which can generate an output reset. The duration
and functionof thisreset is identical to a reset gen-
erated by a power cycle. Table 13 and Figure 14
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than t
R
will not generate a re-
set condition. RSTIN is internally pulled up to V
CC
through a 100K
resistor.
CALIBRATING THE CLOCK
The M48T513Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25
°
C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25
°
C, which equates to about * 1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than 4ppm at 25
°
C. The oscillation rate of crystals
changes with temperature. The M48T513Y/V de-
sign employs periodic counter correction. The cal-
ibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage,
as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed intothe five Calibrationbits foundin theControl
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down. The Calibra-
tion bitsoccupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; ’1’indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles.
If a binary ’1’ is loaded into the register, only the
first 2 minutes inthe 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 os-
cillator cycles for every 125, 829, 120 actual oscil-
lator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration
register. Assuming that the oscillator is running at
exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month. Figure
11 illustrates a TIMEKEEPER calibration wave-
form.
Two methods are available for ascertaining how
much calibration a given M48T513Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recordingdeviation over a fixed
period of time.
Calibration values, including the number of sec-
onds lost or gained in a given period, canbe found
in Application Note: TIMEKEEPER CALIBRA-
TION.
Figure 10. Chip Enable Controlled, Write AC Waveforms
AI02582
tAVAV
tEHAX
tDVWH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEL
tAVWL
tELEH
tWHDX
DATA INPUT
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