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参数资料
| 型号： | M48T513V-85CS1 |
| 厂商： | 意法半导体 |
| 英文描述： | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| 中文描述： | 3.3 - 5V的4兆位的SRAM 512KB的x8计时器 |
| 文件页数： | 6/23页 |
| 文件大小： | 145K |
| 代理商： | M48T513V-85CS1 |
M48T513Y, M48T513V
6/23
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted beforeclock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cellsin the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register (7FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count;that is, the day,date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ bit is reset to a ’0’.
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 11).
Resetting the WRITE bit to a ’0’then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to theactual TIMEKEEPER countersand
allows normal operation to resume. After the
WRITE bit is reset, the nextclock update willoccur
approximately one second later.
Note:
Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 7FFF9h. Setting it to
a ’1’ stops the oscillator. When reset to a ’0’, the
M48T513Y/V oscillator starts within one second.
Note:
It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
SETTING ALARM CLOCK
Registers 7FFF6h-7FFF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be pro-
grammed to go off while the M48T513Y/V is in the
battery back-upto serve as a system wake-upcall.
Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 12 shows the possible config-
urations.Codes not listedin the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note:
Usermust transition address(or toggleChip
Enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register as shown in Figure 12. A subse-
quent read of the Flags register will reset the
Alarm Flag (D6; Register 7FFF0h).
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable)and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. Theuser can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T513Y/V was in the deselect mode
during power-up. Figure 13 illustrates the back-up
mode alarm timing.
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. Bits BMB4-BMB0 storeabinary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within
±
the selected
resolution.
相关PDF资料 |
PDF描述 |
|---|---|
| M48T513V-85PM1 | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513VSH | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T559YSH | Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Yellow; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
| M48T559 | 64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T559YMH1 | MOD. CONN, M,RJ-11, 6WIRE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T513V-85PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513VPM | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513VSH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y-70CS1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
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