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参数资料
| 型号： | M48T559YMH |
| 厂商： | 意法半导体 |
| 英文描述： | 64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| 中文描述： | 64千位8KB的x8 SRAM的计时与地址/数据复用 |
| 文件页数： | 9/18页 |
| 文件大小： | 147K |
| 代理商： | M48T559YMH |
9/18
M48T559Y
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T559Y is
shipped from STMicroelectronics with the STOP
bit set to a ’1’. When reset to a ’0’, the M48T559Y
oscillator starts within one second.
Calibrating the Clock
The M48T559Y is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768Hz. The
devices are tested not to exceed 35 ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M48T559Y improves to better than ±4 ppm
at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T559Y design, however, employs period-
ic counter correction. The calibration circuit adds
or subtracts counts from the oscillator divider cir-
cuit at the divide by 256 stage, as shown in Figure
9. The number of times pulses are blanked (sub-
tracted, negative calibration) or split (added, posi-
tive calibration) depends upon the value loaded
into the five bit Calibration byte found in the Con-
trol Register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a '1' is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a '1' remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0'.
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WRITE bit to a '1', like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 9). Resetting the WRITE bit to a
'0' then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur in one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Figure 8. Clock Calibration
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T559YMH1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T559Y-MH1 | 功能描述:RAM其它 8KX8 TIMEKEEPR RoHS:否 制造商:Freescale Semiconductor 封装:Tray |
| M48T559YMH1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T559YSH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
| M48T58 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
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