参数资料
型号: M48T559YSH
厂商: 意法半导体
英文描述: Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Yellow; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
中文描述: 64千位8KB的x8 SRAM的计时与地址/数据复用
文件页数: 12/18页
文件大小: 147K
代理商: M48T559YSH
M48T559Y
12/18
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Register (Ad-
dress 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x
1 or 3 seconds).
Note
: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T559Y sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0', the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a '1', the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register will
reset to a '0' at the end of a watchdog time-out
when the WDS bit is set to a '1'.
The watchdog timer can be reset by two methods:
– a transition (high-to-low or low-to-high) can be
applied to the Watchdog input pin (WDI)
or
– the microprocessor can perform a write of the
Watchdog Register. The time-out period then
starts over The WDI pin contains a pull-up resis-
tor and therefore can be left unconnected if not
used.
The watchdog timer will be reset on each transition
(edge) seen by the WDI pin. In order to perform a
software reset of the Watchdog timer, the original
time-out period can be written into the Watchdog
Register, effectively restarting the count-down cy-
cle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (D7; Register MSB-
15).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Figure 11. Back-up Mode Alarm Waveforms
AI01678C
VCC
VPFD (max)
VPFD (min)
IRQ/FT
HIGH-Z
AFE bit in Interrupt Register
AF bit in Flags Register
HIGH-Z
VSO
tREC
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