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参数资料
| 型号： | M48T59V-70MH6E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO28 |
| 封装： | 0.330 INCH, LEAD FREE, PLASTIC, SOH-28 |
| 文件页数： | 9/29页 |
| 文件大小： | 440K |
| 代理商： | M48T59V-70MH6E |
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M48T59, M48T59Y, M48T59V*
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register (Ad-
dress 1FF7h). The five bits (BMB4-BMB0) that
store a binary multiplier and the two lower order
bits (RB1-RB0) select the resolution, where
00 = 1/16 second, 01 = 1/4 second, 10 = 1 sec-
ond, and 11 = 4 seconds. The amount of time-out
is then determined to be the multiplication of the
five-bit multiplier value with the resolution. (For ex-
ample: writing 00001110 in the Watchdog Regis-
ter = 3 x 1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T59/Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FF0h).
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0,' the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a '1,' the watchdog will
output a negative pulse on the RST pin for a dura-
tion of trec. The Watchdog Register, the FT Bit, and
the AFE and ABE Bits will reset to a '0' at the end
of a watchdog time-out when the WDS bit is set to
a '1.'
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register.
The time-out period then starts over. The watch-
dog timer is disabled by writing a value of
00000000 to the eight bits in the Watchdog Regis-
ter.
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Power-on Reset
The M48T59/Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for trec after VCC passes VPFD (max).
RST is valid for all VCC conditions. The RST pin is
an open drain output and an appropriate resistor to
VCC should be chosen to control rise time.
Programmable Interrupts
The M48T59/Y/V provides two programmable in-
terrupts; an alarm and a watchdog. When an inter-
rupt condition occurs, the M48T59/Y/V sets the
appropriate flag bit in the Flag Register 1FF0h.
The interrupt enable bits in (AFE and ABE) in
1FF6h and the Watchdog Steering (WDS) Bit in
1FF7h allow the interrupt to activate the IRQ/FT
pin.
The Alarm flag and the IRQ/FT output are cleared
by a READ to the Flags Register. An interrupt con-
dition reset will not occur unless the addresses are
stable at the flag location for at least 15ns while
the device is in the READ Mode as shown in Fig-
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10k
recommended) to
VCC. The pin remains in the high impedance state
unless an interrupt occurs or the Frequency Test
Mode is enabled.
Battery Low Flag
The M48T59/Y/V automatically performs periodic
battery voltage monitoring upon power-up and at
factory-programmed time intervals of 24 hours (at
day rollover) as long as the device is powered and
the oscillator is running. The Battery Low Flag
(BL), Bit D4 of the Flags Register 1FF0h, will be
asserted high if the internal or SNAPHAT battery
is found to be less than approximately 2.5V. The
BL Flag will remain active until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery voltage is
below 2.5V (approximately), which may be insuffi-
cient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates the battery is
near end of life. However, data has not been com-
promised due to the fact that a nominal VCC is sup-
plied. In order to insure data integrity during
subsequent periods of battery back-up mode, it is
recommended that the battery be replaced. The
SNAPHAT top may be replaced while VCC is ap-
plied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T59/Y/V
only monitors the battery when a nominal VCC is
applied to the device. Thus applications which re-
quire extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is in-
dicated, data integrity should be verified upon
power-up via a checksum or other technique.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T59V-70MH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T59V-70PC1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
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