参数资料
型号: M4A3-96/48-55VC
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 5.5 ns, PQFP100
封装: TQFP-100
文件页数: 2/62页
文件大小: 1078K
代理商: M4A3-96/48-55VC
10
ispMACH 4A Family
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
SWAP
D/T/L
Q
AP
AR
Power-Up
Reset
PAL-Block
Initialization
Product Terms
From Logic Allocator
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Output and Input
Switch Matrices
Common PAL-block resource
Individual macrocell resources
From
PAL-Clock
Generator
D/T/L
Q
AP
AR
Power-Up
Reset
Individual
Initialization
Product Term
From Logic
Allocator
Block CLK0
Block CLK1
To Output and Input
Switch Matrices
Individual Clock
Product Term
From PAL-Block
Clock Generator
SWAP
17466G-010
Figure 5. Macrocell
17466G-009
a. Synchronous mode
b. Asynchronous mode
相关PDF资料
PDF描述
M4A3-96/48-7VC High Performance E 2 CMOS In-System Programmable Logic
M4A3-96/48-7VI High Performance E 2 CMOS In-System Programmable Logic
M4A5-64/32-12VI48 High Performance E 2 CMOS In-System Programmable Logic
M4A5-64/32-55JC High Performance E 2 CMOS In-System Programmable Logic
M4A5-64/32-55VC High Performance E 2 CMOS In-System Programmable Logic
相关代理商/技术参数
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M4A453015 制造商:Panasonic Industrial Company 功能描述:ESCUTCHEON SUB: M4A453015A
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