参数资料
型号: M4A5-128/64-10VI
厂商: Lattice Semiconductor Corporation
文件页数: 9/62页
文件大小: 0K
描述: IC CPLD ISP 4A 128MC 100TQFP
标准包装: 90
系列: ispMACH® 4A
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 4.5 V ~ 5.5 V
宏单元数: 128
输入/输出数: 64
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
ispMACH 4A Family
17
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and
flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable
product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type
register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of
the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed”
data comparison, where the first data value is stored, and then the second data value is put on the I/O pin
and compared with the previous stored value.
Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells.
It powers up to a logic low.
Zero-Hold-Time Input Register
The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with
loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path
setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased,
the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs
for which data is loaded from sources which have low (or zero) minimum output propagation delays from
clock edges.
D/L
Q
Block CLK3
Block CLK2
Block CLK1
Block CLK0
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
17466G-017
17466G-018
Figure 10. I/O Cell for ispMACH 4A Devices with 2:1
Macrocell-I/O Cell Ratio
Figure 11. I/O Cell for ispMACH 4A Devices with 1:1
Macrocell-I/O Cell Ratio
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
Power-up reset
相关PDF资料
PDF描述
GRM42A7U3F101JW31L CAP CER 100PF 3.15KV 5% U2J 1808
MIC37151-1.65BR IC REG LDO 1.65V 1.5A SPAK-5
MIC2589-2BM IC CTRLR HOT SWAP NEG HV 14-SOIC
MIC37151-1.5BR TR IC REG LDO 1.5V 1.5A SPAK-5
MIC37150-3.3BR TR IC REG LDO 3.3V 1.5A S-PAK-3
相关代理商/技术参数
参数描述
M4A5-192/96-10VC 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
M4A5-192/96-10VI 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
M4A5-192/96-10VNC 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
M4A5-192/96-10VNI 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
M4A5-192/96-12VI 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100