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参数资料
| 型号： | M4A5-96/48-12VNI |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 56/62页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 96MACRO 100TQFP |
| 标准包装： | 450 |
| 系列： | ispMACH® 4A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 12.0ns |
| 电压电源 - 内部： | 4.5 V ~ 5.5 V |
| 宏单元数： | 64 |
| 输入/输出数： | 48 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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6
ispMACH 4A Family
Table 4. Architectural Summary of ispMACH 4A devices
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate
with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL blocks through the central switch matrix
so that the designer does not have to be concerned with the internal architecture of the device.
Each PAL block consists of:
◆ Product-term array
◆ Logic allocator
◆ Macrocells
◆ Output switch matrix
◆ I/O cells
◆ Input switch matrix
◆ Clock generator
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
Macrocell-I/O Cell Ratio
2:1
1:1
Input Switch Matrix
Yes
Yes1
Input Registers
Yes
No
Central Switch Matrix
Yes
Output Switch Matrix
Yes
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