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参数资料
型号： M4LV-96/48-18VI
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： PLD
英文描述： High Performance E 2 CMOS In-System Programmable Logic
中文描述： EE PLD, 18 ns, PQFP100
封装： TQFP-100
文件页数： 22/46页
文件大小： 754K
代理商： M4LV-96/48-18VI
MACH 4 Family
29
BLOCK DIAGRAM – M4(LV)-256/128
Central
Switch
Matrix
Block B
I/O8–I/O15
CLK0–CLK3
I/O48–I/O55
Block G
I/O72–I/O79
Block J
I/O64–I/O71
Block I
I0–I13
I/O56–I/O63
Block H
Block A
I/O0–I/O7
Block O
I/O112–I/O119
Block P
I/O120–I/O127
Block C I/O16–I/O23
Block D I/O24–I/O31
Block E I/O32–I/O39
Block F I/O40–I/O47
I/O104–I/O111 Block N
I/O96–I/O103 Block M
I/O88–I/O95 Block L
I/O80–I/O87 Block K
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
14
4
OE
8
16
8
4
16
24
8
16
34
4
8
24
34
4
8
16
4
16
OE
8
24
34
4
8
16
4
16
OE
4
8
34
24
16
8
16
8
4
16
OE
4
34
24
16
8
16
4
8
OE
4
34
24
16
8
16
4
8
4
8
34
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
34
4
OE
8
16
8
4
16
24
8
16
34
4
8
24
34
4
8
16
4
16
OE
8
24
34
4
8
16
4
16
OE
4
8
34
24
16
8
16
8
4
16
OE
4
34
24
16
8
16
4
8
OE
4
34
24
16
8
16
4
8
4
8
34
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
34
4
OE
17466G-024
相关PDF资料
PDF描述
M4LV-96/48-7VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-256/128-10YI High Performance E 2 CMOS In-System Programmable Logic
M4LV-64/32-18VI High Performance E 2 CMOS In-System Programmable Logic
M4-256/128-12AC High Performance E 2 CMOS In-System Programmable Logic
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