参数资料
型号: M5-128/68-15VI/1
厂商: Lattice Semiconductor Corporation
文件页数: 40/42页
文件大小: 0K
描述: IC CPLD ISP 128MC 68IO 100TQFP
标准包装: 90
系列: MACH® 5
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 15.0ns
电压电源 - 内部: 4.5 V ~ 5.5 V
宏单元数: 128
输入/输出数: 68
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
MACH 5 Family
7
Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Clock Line 2 Options
Global clock (0, 1, 2, or 3) with clock enable
Clock Line 3 Options
Complement of clock line 2 (same clock enable)
Product-term clock (if clock line 2 does not use clock enable
The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for the PAL
block. Each macrocell can choose one of these three lines or choose no set/reset at all. All three lines can be
configured for product term set/reset and two of the three lines can be configured as sum term set/reset and
one of the lines can be configured as product-term or sum-term latch enable. While the set/reset signals are
generated in the control generator, whether that signal sets or resets a flip-flop is determined within the
individual macrocell. The same signal can set one flip-flop and reset another. PT2 or /PT2 can also be used
as a latch enable for macrocells configured as latches.
0
1
2
3
0
1
2
3
0
1
2
3
CLKIN
Clock Enable
N (0)
N (1)
OUT
MUX 2TO1
/CLK
F0
/CLK
CLK
CLKEN1
BIPHASE
CLKEN2
OUT
CLK0
CLK1
CLK2
CLK3
CLKIN
Clock Enable
MUX 2TO1
/CLK2
PTCLK
F0
Block
Clocks
0–3
PT (0:3)
PINCLK (0:3)
PT0
PT1
PT2
PT3
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U1
F0
F1
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U2
F0
F1
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U3
F0
F1
MUX
2TO1
MUX 2TO1
F0
20446G-004
Figure 4. Clock Generator
SET2/RST2/LE
Block
Sets/Reset
0–2, LE
PT (0:2)
PT0
PT1
PT2
SET1/RST1
SET0/RST0
MUX 2TO1
OUT
F0
PT1
/PT1(ST)
MUX 2TO1
OUT
F0
PT2
/PT2
20446G-005
Figure 5. Set/Reset Generator
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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