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参数资料
| 型号： | M5-256/160-12YC/1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 12/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD ISP 256MC 160IO 208PQFP |
| 标准包装： | 24 |
| 系列： | MACH® 5 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 12.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 宏单元数： | 256 |
| 输入/输出数： | 160 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 包装： | 托盘 |
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2
MACH 5 Family
Note:
1.
“M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
GENERAL DESCRIPTION
The MACH 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic
Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low
power, and supports additional features such as in-system programmability, Boundary Scan testability, and
advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx)
operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies,
MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-
ns devices are compliant with the PCI Local Bus Specification.
Table 1. MACH 5 Device Features 1
Feature
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage (V)
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
Macrocells
128
192
256
320
384
512
Maximum User I/O Pins
120
160
192
160
256
tPD (ns)
5.5
6.5
tSS (ns)
3.0
tCOS (ns)
4.5
5.0
fCNT (MHz)
182
167
Typical Static Power (mA)
35
45
55
70
75
100
IEEE 1149.1 Boundary Scan Compliant
Yes
PCI-Compliant
Yes
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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