- 您现在的位置：买卖IC网 > PDF目录19641 > M5-256/160-12YI/1 (Lattice Semiconductor Corporation)IC CPLD ISP 256MC 160IO 208PQFP PDF资料下载
参数资料
| 型号： | M5-256/160-12YI/1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 34/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD ISP 256MC 160IO 208PQFP |
| 标准包装： | 24 |
| 系列： | MACH® 5 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 12.0ns |
| 电压电源 - 内部： | 4.5 V ~ 5.5 V |
| 宏单元数： | 256 |
| 输入/输出数： | 160 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页第36页第37页第38页第39页第40页第41页第42页
4
MACH 5 Family
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback.
If the I/O is used in another PAL block, the
interconnect feeder assigns a block interconnect line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder assigns block interconnect lines and local
feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相关PDF资料 |
PDF描述 |
|---|---|
| GBM06DRUH | CONN EDGECARD 12POS DIP .156 SLD |
| M5-256/160-10YC/1 | IC CPLD ISP 256MC 160IO 208PQFP |
| GCM02DRTN | CONN EDGECARD 4POS DIP .156 SLD |
| ATF1504ASV-15AI44 | IC CPLD 15NS LOW VOLT 44TQFP |
| MIC5236BM TR | IC REG LDO ADJ .15A 8-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5262-I | 制造商:Leviton Manufacturing Co 功能描述: |
| M5262-IG | 制造商:Leviton Manufacturing Co 功能描述: |
| M5262-IGE | 制造商:Leviton Manufacturing Co 功能描述: |
| M5265P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:LOW SATURATION OUTPUT TYPE CURRENT DRIVER |
| M5266P | 制造商:Panasonic Industrial Company 功能描述:IC |
发布紧急采购，3分钟左右您将得到回复。