- 您现在的位置：买卖IC网 > PDF目录180222 > M5-256/68-7YC (LATTICE SEMICONDUCTOR CORP) Fifth Generation MACH Architecture PDF资料下载
参数资料
| 型号： | M5-256/68-7YC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 16/47页 |
| 文件大小： | 1145K |
| 代理商： | M5-256/68-7YC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页
MACH 5 Family
23
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delay:
tPDi
Internal combinatorial propagation
delay
3.5
4.5
5.5
8.0
10.0
13.0
18.0
ns
tPD
Combinatorial propagation delay
5.5
6.5
7.5
10.0
12.0
15.0
20.0
ns
Registered Delays:
tSS
Synchronous clock setup time
3.0
4.0
5.0
6.0
8.0
10.0
ns
tSA
Asynchronous clock setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHS
Synchronous clock hold time
0.0
ns
tHA
Asynchronous clock hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tCOSi
Synchronous clock to internal output
2.5
3.0
4.0
5.0
6.0
8.0
10.0
ns
tCOS
Synchronous clock to output
4.5
5.0
6.0
7.0
8.0
10.0
12.0
ns
tCOAi
Asynchronous clock to internal output
6.0
8.0
10.0
13.0
15.0
18.0
ns
tCOA
Asynchronous clock to output
8.0
10.0
12.0
15.0
17.0
20.0
ns
Latched Delays:
tSAL
Latch setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHAL
Latch hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tPDLi
Transparent latch internal
6.0
7.0
8.0
9.0
10.0
ns
tPDL
Propagation delay through transparent
latch
8.0
9.0
10.0
11.0
12.0
ns
tGOAi
Gate to internal output
7.0
8.0
9.0
10.0
11.0
12.0
ns
tGOA
Gate to output
9.0
10.0
11.0
12.0
13.0
14.0
ns
Input Register Delays:
tSIRS
Input register setup time using a
synchronous clock
2.0
3.0
ns
tSIRA
Input register setup time using an
asynchronous clock
0.0
ns
tHIRS
Input register hold time using a
synchronous clock
3.0
4.0
ns
tHIRA
Input register hold time using an
asynchronous clock
6.0
7.0
ns
Input Latch Delays:
tSIL
Input latch setup time
2.0
3.0
ns
tHIL
Input latch hold time
6.0
7.0
ns
tPDILi
Transparent input latch
5.0
5.5
6.0
ns
Output Delays:
tBUF
Output buffer delay
2.0
ns
tSLW
Slow slew rate delay
2.5
ns
tEA
Output enable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
tER
Output disable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
相关PDF资料 |
PDF描述 |
|---|---|
| M5-256/68-7YI | Fifth Generation MACH Architecture |
| M5-320/160-15HC | Fifth Generation MACH Architecture |
| M5-320/160-15HI | Fifth Generation MACH Architecture |
| M5-320/160-7HC | Fifth Generation MACH Architecture |
| M5-320/160-7HI | Fifth Generation MACH Architecture |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5262-I | 制造商:Leviton Manufacturing Co 功能描述: |
| M5262-IG | 制造商:Leviton Manufacturing Co 功能描述: |
| M5262-IGE | 制造商:Leviton Manufacturing Co 功能描述: |
| M5265P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:LOW SATURATION OUTPUT TYPE CURRENT DRIVER |
| M5266P | 制造商:Panasonic Industrial Company 功能描述:IC |
发布紧急采购，3分钟左右您将得到回复。