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参数资料
| 型号： | M5-320/192-12AC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 12 ns, PBGA256 |
| 封装： | BGA-256 |
| 文件页数： | 13/47页 |
| 文件大小： | 1145K |
| 代理商： | M5-320/192-12AC |
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20
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-512/XXX
Macrocells
64
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73
AND
Logic
Array
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Logic
Allocator
Control
Generator
64
PT
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OE
I/O
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32
7
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32
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Macrocells
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Logic
Array
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Logic
Allocator
Control
Generator
64
PT
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I/O
Cells
16
32
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Macrocells
Control
Generator
64
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OE
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Cells
64
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AND
Logic
Array
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Logic
Allocator
Macrocells
Control
Generator
64
PT
2
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OE
16
32
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32
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I/O
Cells
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Block
A/Macrocells
0-15
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D/Macrocells
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Interconnect
Macrocells
64
x
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AND
Logic
Array
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Logic
Allocator
Control
Generator
64
PT
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I/O
Cells
16
32
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PT
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2
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Macrocells
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73
AND
Logic
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Logic
Allocator
Control
Generator
64
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I/O
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16
32
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Macrocells
Control
Generator
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Generator
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Interconnect
Macrocells
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32
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Macrocells
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Generator
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Macrocells
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Generator
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Logic
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Control
Generator
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32
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Cells
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AND
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Logic
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A/Macrocells
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D/Macrocells
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B/Macrocells
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C/Macrocells
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Interconnect
Macrocells
64
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73
AND
Logic
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Allocator
Control
Generator
64
PT
2
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I/O
Cells
16
32
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2
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Macrocells
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Macrocells
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Interconnect
IN
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SEGMENT
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SEGMENT
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SEGMENT
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SEGMENT
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I 3
I 2
20446G-013
Continued
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