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参数资料
| 型号： | M50FW016N1 |
| 厂商： | 意法半导体 |
| 英文描述： | 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，统一座3V电源闪存固件集线器 |
| 文件页数： | 4/45页 |
| 文件大小： | 673K |
| 代理商： | M50FW016N1 |
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M50FW016
12/45
programming. Only a subset of the features
available to the Firmware Hub (FWH) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface
is
selected
all
the
blocks
are
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
be High, VIH, and Output Enable, G, Low, VIL, in
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
Characteristics, for details of when the output
becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Interface Reset, RP, must be High, VIH and Write
Enable, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write
Enable, W. See Figure 14., A/A Mux Interface
Interface Write AC Characteristics, for details of
the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL,
during a Program
or Erase operation,
the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to tPLRH to abort a Program or Erase operation.
相关PDF资料 |
PDF描述 |
|---|---|
| M50FW016N1G | 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N1TG | 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N5 | 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N5G | 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW080K1 | 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FW016N1G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N1TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50FW016N5G | 功能描述:闪存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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