参数资料
型号: M5253DEMO
厂商: Freescale Semiconductor
文件页数: 9/14页
文件大小: 0K
描述: DEMO BOARD FOR MCF5253
标准包装: 1
系列: ColdFire®
类型: MCU
适用于相关产品: MCF5253
所含物品:
Hardware Submodules
also routed out at the serial connector J17 for customer use. Customer can use the on-board jumpers J5 and
J27 to control the analog input of each channel.
3.18
CAN Interface
The MCF5253 has two CAN-bus interfaces. The M5253 demo board provides one CAN transceiver with
a DB9 connector. There is a 120 ? loopback load resistor, which represents the impedance of the system
on the CAN bus.
3.19
Power Regulation
The M5253 demo board provides a Freescale QuiccSupply MC34702 power regulator. The MC34702 is
Freescale’s power management IC, which incorporates a high-performance switching regulator and a
low-dropout (LDO) linear-regulator control circuit. This power regulator provides a 3.3 V voltage by
switching the regulator module for the microprocessor I/O and bus voltage and 1.2 V voltage from LDO
for the CPU-core voltage supply. The regulator generates these voltages from a 5 V external supply.
The 5 V supply can be provided through the power-jack connector. The MCF5253 has an internal LDO
that can also generate a 1.2 V voltage and the J15 is to select which of the 1.2 V voltages is to be used.
3.20
Boot Options
The MCF5253 has two boot options:
? Booting from the FlexBus CS0/CS4 with default boot options.
? Booting from the internal bootROM and override defaults with the serial-boot facility.
The boot mode is determined by the logic level of the pin A23 during the powerup reset. When the A23 is
pulled up during the powerup, the CPU will boot from the memory connected to the CS0/CS4, which is
the flash on the M5253 demo board. The J21 on the board selects the boot option.
When the A23 is pulled down during the powerup, the CPU will boot from the on-chip boot ROM. The
GPIO48~50 pin’s logic will be sensed at the powerup to decide further boot options. On the M5253 demo
board, the J29, J31, and J30 are to select the logic of the GPIO48~50. Here is the boot table:
Table 4. Boot Options of the On-Chip ROM
BOOT MODE
GPIO50/PST0 (J30) GPIO49/PST1 (J31) GPIO48/PST2 (J29)
*I 2 C master (default)*
SPI master
IDE master
I 2 C slave
UART (5.6448/11.2896 MHz)
UART (8.4672/16.9344/
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
33.8688 MHz)
UART (5/10/20 MHz)
1
1
1
* - means default setting, 0 - means the signal to be pulled to ground, 1 - means the signal to be pulled high
M5253 Demo Board User Manual, Rev. 0
Freescale Semiconductor
9
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