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参数资料
| 型号： | M54HC4094F1R |
| 厂商： | 意法半导体 |
| 英文描述： | 8 BIT SIPO SHIFT LATCH REGISTER 3-STATE |
| 中文描述： | 8位国家知识产权局位移锁存寄存器三态 |
| 文件页数： | 1/12页 |
| 文件大小： | 270K |
| 代理商： | M54HC4094F1R |
M54HC4094
M74HC4094
February 1993
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 4094B
B1R
(Plastic Package)
ORDER CODES :
M54HC4094F1R
M74HC4094B1R
M74HC4094M1R
M74HC4094C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
The M54/74HC4094 is a high speed CMOS 8 BIT
SIPOSHIFTLATCH REGISTERfabricated withsili-
con gate C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device consists of an 8-bit shift register and an
8-bit latch with 3-state output buffer. Data is shifted
serially through the shift register on the positive
going transition of the clockinput signal. The output
of the last stage (Qs) can be used to cascade sev-
eral devices.
DataontheQsoutputistransferred toa secondout-
put (Qs’) on the following negative transition of the
clockinputsignal. Thedataof eachstageofthe shift
register is provided with a latch, which latches data
on the negative going transition of the STROBE
input signal. When the STROBE input is heldhigh,
datapropagates throughthelatchtoa3-stateoutput
buffer.
This buffer is enabled when OUTPUT ENABLE
input is takenhigh. Allinputsare equipped with pro-
tectioncircuitsagainst staticdischarge and transient
excess voltage.
.
HIGH SPEED
f
MAX
= 73 MHz (TYP.) AT V
CC
= 5 V
1/12
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