参数资料
型号: M54HC590
厂商: 意法半导体
元件分类: 通用总线功能
英文描述: 8 BIT BINARY COUNTER REGISTER (3 STATE)
中文描述: 8位二进制计数器寄存器(3态)
文件页数: 1/14页
文件大小: 289K
代理商: M54HC590
M54HC590
M74HC590
March 1993
8 BIT BINARY COUNTER REGISTER (3 STATE)
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS (forRCO)
15 LSTTL LOADS (forQA
QH)
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6mA(MIN.)FORQA~QHOUTPUT
I
OH
=
I
OL
= 4 mA(MIN.) FOR RCO OUTPUT
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS590
B1R
(Plastic Package)
ORDER CODES :
M54HC590F1R
M74HC590B1R
M74HC590M1R
M74HC590C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
.
HIGH SPEED
f
MAX
= 62 MHz (TYP.) AT V
CC
= 5 V
DESCRIPTION
The M54/74HC590 isa highspeed CMOS8-BIT BI-
NARY COUNTER REGISTER (3-STATE) fabri-
cated in silicon gate C
2
MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption.
These devices each contain an 8-bit binary counter
that feeds an8-bit storage register. Thestoragereg-
ister has parallel outputs. Separate clocks are pro-
vided for both the binary counter and storage
register. The binary counter features a direct clear
input CCLR and a count enable input CCKEN. For
cascading, a ripple carry output RCO is provided.
Expansion is easily accomplished by tying RCO of
the first stage to CCKEN of the second stage, etc.
Both the counter and register clocks are positive-
edge triggered. If the user wishes to connect both
clockstogether, thecounter statewill always be one
count ahead of the register. Internal circuitry pre-
vents clocking fromthe clock enable.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
1/14
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