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参数资料
| 型号： | M54HC696 |
| 厂商： | 意法半导体 |
| 元件分类： | 通用总线功能 |
| 英文描述： | Decade Up/Down Counter/Register(十进制加/减计数器/寄存器(三态)) |
| 中文描述： | 十年加/减计数器/寄存器（十进制加/减计数器/寄存器（三态）） |
| 文件页数： | 15/22页 |
| 文件大小： | 429K |
| 代理商： | M54HC696 |
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
45
15
13
57
19
16
32
17
14
40
-55 to 125
o
C
54HC
Min.
Max.
120
24
20
150
30
26
115
23
20
75
15
13
75
15
13
50
10
9
150
30
26
50
10
9
100
20
17
100
20
17
5
5
5
5
5
5
10
Max.
150
30
26
190
38
32
145
29
25
95
19
16
95
19
16
65
13
11
190
38
32
65
13
11
125
25
21
125
25
21
5
5
5
5
5
5
10
Max.
180
36
31
225
45
38
175
35
30
110
22
19
110
22
19
75
15
13
220
44
37
75
15
13
150
30
26
145
29
25
5
5
5
5
5
5
10
t
PZL
t
PZH
Output Enable
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
R
L
= 1K
ns
150
R
L
= 1K
ns
t
PLZ
t
PHZ
Output Disable
Time
50
R
L
= 1K
ns
t
W(H)
t
W(L)
Minimum Pulse
Width
(CCK, RCK)
50
ns
8
7
t
W(L)
Minimum Pulse
Width
(CCLR)
50
for
HC696
HC697
40
8
7
16
4
3
64
16
14
16
4
3
44
11
9
44
11
9
ns
t
s
Minimum Set-up
Time
(CCLR)
50
for
HC698
HC699
ns
t
s
Minimum Set-up
Time (LOAD,
ENT, ENP)
50
ns
t
s
Minimum Set-up
Time
(A, B, C, D)
50
ns
t
s
Minimum Set-up
Time
(CCK, RCK)
50
ns
t
s
Minimum Set-up
Time
(U/D)
50
ns
t
h
Minimum Hold
Time
50
ns
t
REM
Minimum
Removal Time
50
for
HC696
HC697
ns
C
IN
Input Capacitance
Power Dissipation
Capacitance
5
pF
C
PD
(*)
HC696/697/699
HC698
71
77
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2(per circuit)
AC ELECTRICAL CHARACTERISTICS
(Continued)
M54/M74HC696/697/698/699
15/22
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