参数资料
型号: M58WR064HU70ZB6U
元件分类: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封装: 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件页数: 16/117页
文件大小: 2300K
代理商: M58WR064HU70ZB6U
Command interface state tables
M58WR064HU M58WR064HL
112/117
Appendix D
Command interface state tables
Table 43.
Command interface states - modify table, next state
Current CI State
Command Input(1)
Read
Array(2)
(FFh)
WP
setup(3)(4)
(10/40h)
DWP,
QWP
Setup(3)(4)
(35h, 56h)
Block
Erase,
Bank
Erase
Setup(3)(4)
(20h, 80h
EFP
Setup
(30h)
Quad-
EFP
Setup
(75h)
Erase
Confirm
P/E Resume,
Block Unlock
confirm, EFP
Confirm
(D0h)
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
status
Register
(5) (50h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
Ready
Ready
Program
Setup
Program
Setup
Erase
Setup
EFP
Setup
Quad-
EFP
Setup
Ready
Lock/CR Setup
Ready (Lock Error)
Ready
Ready (Lock Error)
OTP
Setup
OTP Busy
Busy
Program
Setup
Program Busy
Busy
Program Busy
Program
Suspended
Program Busy
Suspend
Program Suspended
Program Busy
Program Suspended
Erase
Setup
Ready (error)
Erase Busy
Ready (error)
Busy
Erase Busy
Erase
Suspended
Erase Busy
Suspend
Erase
Suspended
Program
in Erase
Suspend
Erase Suspended
Erase Busy
Erase Suspended
Program
in Erase
Suspend
Setup
Program Busy in Erase Suspend
Busy
Program Busy in Erase Suspend
Program
Suspend in
Erase
Suspend
Program Busy in Erase Suspend
Suspend
Program Suspend in Erase Suspend
Program Busy
in Erase
Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in
Erase Suspend
Erase Suspend (Lock Error)
Erase
Suspend
Erase Suspend (Lock Error)
EFP
Setup
Ready (error)
EFP Busy
Ready (error)
Busy
EFP Busy(6)
Verify
EFP Verify(6)
Quad
EFP
Setup
Quad EFP Busy(6)
Busy
Quad EFP Busy(6)
1.
CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory
Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.
2.
At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output.
3.
The two cycle command should be issued to the same bank address.
4.
If the P/E.C. is active, both cycles are ignored.
5.
The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6.
EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is first EFP
Address. Any other commands are treated as data.
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