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参数资料
| 型号： | M5M44260CJ-7 |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| 中文描述： | 快速页面模式4194304位（262144字由16位）动态随机存储器 |
| 文件页数： | 29/29页 |
| 文件大小： | 283K |
| 代理商： | M5M44260CJ-7 |
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FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44260CJ,TP-5,-5S : Under development
All combination of nine row address signals (A
0
~A
8
) are
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write
Self Refresh
Read / Write
t
NSB
t
RASS
≥
100μs
t
SNB
last
refresh Cycles
first
refresh cycles
Table 3
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
t
NSB
+t
SNB
≤
8.2ms
Definition of CBR burst refresh
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
Switching from read/write operation to self refresh operation.
The time interval t
NSB
from the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval t
SNB
from the rising edge of RAS signal at
the end of self refresh operation to the falling edge of RAS
signal in the last CBR refresh cycle during read/write operation
period should be set within 8.2 ms.
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the
first RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within t
NSB
(shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in
the last RAS only refresh cycle during read/write operation
period should be set within t
SNB
(shown in table 3).
RAS
refresh cycles
511 cycles
refresh cycles
511 cycles
(B) Definition of burst refresh
8.2ms
read/write cycles
RAS
refresh cycles
512 cycles
2.2 RAS only burst refresh
2.1 CBR burst refresh
Definition of RAS only burst refresh
29
t
SNB
≤
8.2ms
t
NSB
≤
8.2ms
Read / Write
Self Refresh
Self Refresh
Read / Write
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相关代理商/技术参数 |
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|---|---|
| M5M44260CJ-7S | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44260CTP-5 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44260CTP-5S | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44260CTP-6 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44260CTP-6S | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
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