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参数资料
| 型号： | M5M44260CTP-6S |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| 中文描述： | 快速页面模式4194304位（262144字由16位）动态随机存储器 |
| 文件页数： | 4/29页 |
| 文件大小： | 283K |
| 代理商： | M5M44260CTP-6S |
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FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44260CJ,TP-5,-5S : Under development
4
Note 6: An initial pause of 500 μs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 2TTL loads and 100pF.
8: Assumes that
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
.
9: Assumes that
t
RCD
≤
t
RCD(max)
and
t
RAD
≤
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that
t
RCD
exceeds the value shown.
10: Assumes that
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
.
11: Assumes that
t
CP
≤
t
CP(max)
and
t
ASC
≥
t
ASC(max)
.
12:
t
OFF(max)
and
t
OEZ (max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
±10 μA ) and is not reference to V
OH(min)
or V
OL(max)
.
SWITCHING CHARACTERISTICS
(Ta=0~70C, V
CC
=5V±10%, Vss=0V, unless otherwise noted, see notes 6,13,14)
Limits
Min
Max
13
50
Parameter
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
Unit
Min
Max
15
60
Min
Max
20
70
ns
ns
ns
ns
ns
ns
ns
ns
5
30
35
15
15
15
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
(Note 12)
(Note 12)
5
5
25
30
13
13
13
35
40
20
20
20
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
CAPACITANCE
Limits
Typ
Min
Max
5
7
Unit
pF
pF
pF
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
C
I (A)
C
I (CLK)
C
I / O
Symbol
Parameter
Test conditions
7
V
I
=V
SS
f=1MHz
V
I
=25mVrms
(Ta=0~70C , V
CC
=5V±10%, V
SS
=0V, unless otherwise noted)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M5M44260CTP-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44260CTP-7S | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44265CJ | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44265CJ-5 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44265CJ-5S | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
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