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参数资料
| 型号： | M5M44800CJ-5S |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| 中文描述： | 快速页面模式4194304位（524288 - Word的8位）动态随机存储器 |
| 文件页数： | 4/21页 |
| 文件大小： | 202K |
| 代理商： | M5M44800CJ-5S |
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44800CJ,TP-5,-5S:Under development
4
SWITCHING CHARACTERISTICS
(Ta=0~70C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,13,14)
Parameter
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
Symbol
ns
ns
ns
ns
ns
ns
ns
ns
15
60
30
35
15
13
50
25
30
13
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
(Note 12)
(Note 12)
Limits
Unit
Min
Max
M5M44800C-5,-5S M5M44800C-6,-6S
Min
Max
M5M44800C-7,-7S
Min
20
70
35
40
20
Max
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
5
5
5
13
13
15
15
20
20
Note 6:An initial pause of 500μs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of RAS
inactivity before proper device operation is achieved.
Note
7:Measured with a load circuit equivalent to 2TTL loads and 100pF.
Note
8:Assumes that
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
.
Note
9:Assumes that
t
RCD
≤
t
RCD(max
) and
t
RAD
≤
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will
increase by amount that
t
RCD
exceeds the value shown.
nOR
10:Assumes that
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
.
Note
11:Assumes that
t
CP
≤
t
CP(max)
and
t
ASC
≥
t
ASC(max)
.
Note
12:
t
OFF(max)
,
t
OEZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
±10μA ) and is not reference to V
OH(min)
or
V
OL(max)
.
CAPACITANCE
Limits
Typ
Min
Max
5
7
7
Unit
pF
pF
pF
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
C
I (A)
C
I (CLK)
C
I / O
Symbol
Parameter
Test conditions
V
I
=V
SS
f=1MHz
V
I
=25mVrms
(Ta=0~70C, V
CC
=5V±10%, V
SS
=0V, unless otherwise noted)
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