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参数资料
| 型号： | M5M44800CTP-5S |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| 中文描述： | 快速页面模式4194304位（524288 - Word的8位）动态随机存储器 |
| 文件页数： | 5/21页 |
| 文件大小： | 202K |
| 代理商： | M5M44800CTP-5S |
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44800CJ,TP-5,-5S:Under development
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta=0~70C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,13,14)
Note 13: The timing requirements are assumed
t
T
=5ns.
Note
14: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
Note
15:
t
RCD(max)
is specified as a reference point only. If
t
RCD
is less than
t
RCD(max
), access time is
t
RAC
. If
t
RCD
is greater than
t
RCD(max)
, access time is
controlled exclusively by
t
CAC
or
t
AA
.
Note
16:
t
RAD(max)
is specified as a reference point only. If
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
, access time is controlled exclusively by
t
AA
.
Note
17:
t
ASC(max)
is specified as a reference point only. If
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
, access time is controlled exclusively by
t
CAC
.
Note
18: Either
t
DZC
or
t
DZO
must be satisfied.
Note
19: Either
t
CDD
or
t
ODD
must be satisfied.
Note
20:
t
T
is measured between V
IH(min)
and V
IL(max)
.
5
Refresh cycle time
Refresh cycle time *
(Note 20)
(Note 15)
(Note 16)
(Note 17)
45
30
0
40
20
5
10
50
10
15
0
0
10
15
0
0
15
1
16.4
128
37
25
0
30
18
5
7
50
10
13
8
13
0
0
1
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Transition time
(Note 18)
(Note 19)
(Note 19)
Delay time, CAS high to data
Delay time, OE high to data
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
0
0
15
13
13
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
35
0
50
20
10
50
5
10
15
10
15
0
0
1
0
0
20
20
t
REF
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
CDD
t
ODD
t
T
Parameter
Symbol
Limits
Unit
Min
Max
M5M44800C-5,-5S M5M44800C-6,-6S
Min
Max
16.4
128
M5M44800C-7,-7S
Min
Max
16.4
128
Read and Refresh Cycles
Note 21: Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
0
(Note 21)
(Note 21)
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
CAS hold time after OE low
Read Setup time before CAS low
0
RAS hold time after OE low
10000
10000
10000
10000
90
50
13
50
13
0
25
13
13
0
0
110
60
15
60
15
0
30
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
0
0
130
70
20
70
20
0
35
20
20
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
OCH
t
ORH
Parameter
Symbol
Limits
Unit
Min
Max
M5M44800C-5,-5S M5M44800C-6,-6S
Min
Max
M5M44800C-7,-7S
Min
Max
(Note 18)
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