参数资料
型号: M5M465165BJ
厂商: Mitsubishi Electric Corporation
英文描述: EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 江户模式67108864位(16777216 - Word的4位)动态随机存储器
文件页数: 11/39页
文件大小: 403K
代理商: M5M465165BJ
MITSUBISHI
ELECTRIC
Jun. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.1)
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
11
Write Cycle (Early Write and Delayed Write)
Parameter
Symbol
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Limits
Unit
M5M46X405B-5,5S
M5M46X805B-5,5S
M5M465165B-5,5S
M5M46X405B-6,6S
M5M46X805B-6,6S
M5M465165B-6,6S
OE hold time after W low
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
t
RWC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
(Note23)
(Note24)
(Note24)
44
0
32
77
47
15
44
38
0
28
65
40
13
109
75
38
70
t
CWD
t
RWD
t
AWD
t
OEH
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
(Note24)
10000
10000
10000
10000
133
89
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Min
Max
Write cycle time
RAS low pulse width
CAS low pulse width
t
WC
t
RAS
t
CAS
8
8
8
t
CSH
t
RSH
t
WCS
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
(Note 24)
t
WCH
t
CWL
t
RWL
t
WP
0
t
DS
t
DH
10000
10000
10000
10000
84
50
8
35
13
8
0
8
10
10
10
0
104
60
10
40
15
10
0
10
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Min
Max
Min
Max
ns
Note 23: t
RWC
is specified as t
RWC(min)
=t
RAC(max)
+t
ODD(min)
+t
RWL(min)
+t
RP(min)
+4t
T.
24: t
WCS
, t
CWD
, t
RWD
and t
AWD
and, t
CPWD
are specified as reference points only. If t
WCS
t
WCS(min)
the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If t
CWD
t
CWD(min),
t
RWD
t
RWD (min),
t
AWD
t
AWD(min)
and t
CPWD
t
CPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to V
IH
) is indetermi-
nate.
M5M46X405B-5,5S
M5M46X805B-5,5S
M5M465165B-5,5S
M5M46X405B-6,6S
M5M46X805B-6,6S
M5M465165B-6,6S
相关PDF资料
PDF描述
M5M465405BTP-5 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
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