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参数资料
| 型号： | M5M5Y816WG-70HI |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 中文描述： | 8388608位（524288字由16位）的CMOS静态RAM |
| 文件页数： | 2/10页 |
| 文件大小： | 87K |
| 代理商： | M5M5Y816WG-70HI |
MITSUBISHI ELECTRIC
M5M5Y816WG -70HI, -85HI
2001.05.22 Ver. 0.1
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
2
FUNCTION
The M5M5Y816WG is organized as 524288-words by
16-bit. These devices operate on a single +1.65~2.3V
power supply, and are directly TTL compatible to both
input and output. Its fully static circuit needs no clocks
and no refresh, and makes it useful.
The operation mode are determined by a combination
of the device control inputs BC1 , BC2 , S1, S2 , W
and OE. Each mode is summarized in the function
table.
A write operation is executed whenever the low level
W overlaps with the low level BC1 and/or BC2 and the
low
level
S1
and
the
address(A0~A18) must be set up before the write cycle
and must be stable during the entire cycle.
A read operation is executed by setting W at a high
level and OE at a low level while BC1 and/or BC2 and
S1 and S2 are in an active state(S1=L,S2=H).
When setting BC1 at the high level and other pins are
in an active stage , upper-byte are in a selectable mode
in which both reading and writing are enabled, and lower-
byte are in a non-selectable mode. And when setting
BC2 at a high level and other pins are in an active
stage, lower-byte are in a selectable mode and upper-
byte are in a non-selectable mode.
BLOCK DIAGRAM
high
level
S2.
The
When setting BC1 and BC2 at a high level or S1 at a high
level or S2 at a low level, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by
BC1, BC2 and S1, S2.
The power supply current is reduced as low as 0.5μA(25°C,
typical), and the memory data can be held at +1.3V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
Mode
Non selection
S2
L
W
X
H
X
X
H
X
H
High-Z
High-Z High-Z
Din
Dout
High-Z High-Z
High-Z
High-Z
BC1BC2
X
OE
X
DQ1~8
High-Z
X
X
X
X
Non selection
Non selection
Write
DQ9~16
High-Z Standby
Icc
High-Z Standby
Standby
H
H
H
H
H
X
L
H
X
L
L
H
H
L
H
L
L
L
H
H
H
H
H
L
L
High-Z
High-Z
Active
Active
Active
Active
Active
Read
H
H
H
L
L
L
Active
Active
H
L
High-Z
Din
High-Z
Active
H
L
H
X
H
High-Z
H
L
Dout
H
L
L
Read
Dout
Active
L
Write
Din
H
High-Z
Write
Read
Din
Dout
S1
H
H
X
L
L
L
L
L
L
L
L
L
L
X
X
High-Z
X
X
Non selection
High-Z Standby
L
X
MEMORY ARRAY
524288 WORDS
x 16 BITS
CLOCK
GENERATOR
A
0
A
1
A
17
A
18
S2
BC1
BC2
W
OE
DQ
8
DQ
1
DQ
16
DQ
9
-
Vcc
GND
S1
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