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参数资料
| 型号： | M63160J |
| 厂商： | Renesas Technology Corp. |
| 元件分类： | 基准电压源/电流源 |
| 英文描述： | STEPPING MOTOR DRIVER |
| 中文描述： | 步进电机驱动器 |
| 文件页数： | 11/18页 |
| 文件大小： | 130K |
| 代理商： | M63160J |
M63160J
Rev.1.1, May.21.2004, page 11 of 17
A motor control logic condition and explanation
1, Data setup
1-1, Data taking in: CLK rising edge
1-2, Data input 1: It carries out in order of D15 - >D0.
1-3, Data input 2: A Mode setup is performed after initial setting.
1-4, Every 16 bits, it is a STB signal and it is Closed.
1-5, A data setup of Ch2 For Test is not performed.
1-6, Sync.Rect.Control “Active” At the time of a setup, The inside of Fast Decay performs negative voltage
detection. FET is set to all OFF when current flows in the right direction.
2, RESET terminal
Low: All data reset(All FET OFF)High :Data setup Standby state
When a RESET terminal is set to “L” and a Motor drive is performed, A REST terminal is set to “H” and serial data
is re inputted.
Internal logic reset is Logic composition of a RESET terminal and a Low Voltage detection machine is performed.
When rapid high load is in FB, a Low Voltage detection machine outputs “L”, Internal logic is reset when an output
does not return to less than 1
μ
s at “H.”
RESET terminal “L”
Internal logic will be in an initial state.(All FET serves as all OFF )
A S/W- REG part continues operation.
3, EN terminal
Low: External PWM Mode Slow Decay or Fast Decay
Off Time
Fast Decay Time: Sleep
A current detection condition setup at the time of Decay is performed by Sync.Rect.Control Active or Passive.
However, current detection is effective only at the time of Fast Decay.(Slow is invalid.)
High :Internal PWM Mode Motor drive state FET ON- >OFF - >ON
4, Motor drive
Motor drive :RESET terminal “H” EN terminal “H” It drives after a Mode Data setup.
Motor STOP :RESET terminal “L” is STOP.
RESET terminal “H” EN terminal “L”: It is set to Decay by External PWM Mode. All FETOFF comes after setting
current detection.
EN is not related to “L or H” in early stages. It FET all turns off till control logic initial setting and the completion
of a Mode setting. EN is always after control logic initial setting and the completion of a Mode setting at “L.”, If it
is External PWM Slow Decay Mode, it is Start about Slow Decay.
(It FET all turns off at the time of Fast Decay Mode.)
After control logic initial setting and the completion of a Mode setting, FET is set to being turned on by EN “H”
and it is compulsorily set to Decay Mode by EN “L.”
However, even if a setup of External PWM Slow Decay Mode is EN “L”, it is reflected.
5, Current detection by Decay
The conditions which perform current detection by Decay
Internal PWM: Sync.Rect.EnableControl1 “H”, Inside of Fast Decay in Mixed Decay Mode
External PWM: Sync.Rect.EnableControl1 “H”, Fast Decay Mode
In addition, Decay current detection is not performed on conditions.
Internal PWM: It changes to Decay from FET ON by the current detection COM., Fast Decay Time-OffTime starts
in this stage. It is Start about the current detection in Decay, Fast Decay Time as a trigger. Detection is stopped after
Fast Decay Time completion.
When setting Decay current is detected during Fast Decay time, FET is all turned off only within Fast Decay time.
It is referred to as Slow Decay till OFF Time completion after Fast Decay completion.
External PWM: With EN terminal “L”, it goes into Regeneration Mode compulsorily. Decay current detection is
Started to a trigger for the signal of EN “L.” Detection is continued until the reversal signal from COM comes out.
Decay current detection serves as [EN] STOP by “H”, and FET is turned on
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