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参数资料
| 型号： | M66853J |
| 厂商： | Mitsubishi Electric Corporation |
| 元件分类： | FIFO |
| 英文描述： | SRAM TYPE FIFO MEMORY |
| 中文描述： | FIFO存储器SRAM的类型 |
| 文件页数： | 8/15页 |
| 文件大小： | 118K |
| 代理商： | M66853J |
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
NOTE :
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge for EF to change during the current clock
cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then EF may not
change state untill the next RCLK edge.
Read Cycle Timing
RCLK
EF
REN1
REN2
WEN1
Q0-8
WCLK
t
REF
t
CLK
OE
t
CLKH
t
CLKL
t
ENS
t
ENH
NO OPERATION
t
OHZ
t
SKEW1
(1)
t
REF
t
AC
t
OE
VALID DATA
t
OLZ
WEN2
8
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