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参数资料
| 型号： | M68AW127BL10N6T |
| 厂商： | 意法半导体 |
| 英文描述： | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
| 中文描述： | 1Mbit的128K的× 8，3.0V异步SRAM |
| 文件页数： | 7/20页 |
| 文件大小： | 327K |
| 代理商： | M68AW127BL10N6T |
7/20
M68AW127B
Table 4. Capacitance
Note: 1. Sampled only, not 100% tested.
2. At T
A
= 25°C, f = 1MHz, V
CC
= 3.0V.
Table 5. DC Characteristics
Note: 1. Average AC current, cycling at t
AVAV
minimum.
2. E1 = V
IL
, E2 = V
IH
, V
IN
= V
IH
or V
IL
.
3. E1
≤
0.2V or E2
≥
V
CC
–0.2V, V
IN
≤
0.2V or V
IN
≥
V
CC
–0.2V.
4. Output disabled.
Symbol
Parameter
(1,2)
Test
Condition
Min
Max
Unit
C
IN
Input Capacitance on all pins (except DQ)
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
I
CC1 (1,2)
Supply Current
V
CC
= 3.6V
,
f = 1/t
AVAV
,
I
OUT
= 0mA
70
6.0
15
mA
100
25
35
mA
I
CC2 (3)
Operating Supply Current
V
CC
= 3.6V
,
f = 1MHz
,
I
OUT
= 0mA
70
2
mA
Operating Supply Current
(READ)
V
CC
= 3.6V
,
f = 1MHz
,
I
OUT
= 0mA
100
1.5
5
mA
Operating Supply Current
(WRITE)
10
15
mA
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
–1
1
μA
I
LO (4)
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
–1
1
μA
I
SB
Standby Supply Current
CMOS
V
CC
= 3.6V
,
E1
≥
V
CC
– 0.2V
,
E2
≤
0.2V
,
f = 0
70
2.5
15
μA
100
0.3
10
μA
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input Low Voltage
70
–0.3
0.8
V
100
–0.3
0.6
V
V
OH
Output High Voltage
I
OH
= –1mA
70
2.4
V
100
2.2
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
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